Silicon process technology has advanced significantly in the past decade. However, for the most part, decades-old package technology is often used to package semiconductor dies. In a conventional packaging process, gold wires couple a semiconductor die and a lead frame together in a semiconductor die package. Leads in the lead frame are coupled to the conductive lands on a circuit substrate such as a printed circuit board (PCB).
Advances in semiconductor processing technology, however, have made the parasitics associated with conventional packages more of a performance-limiting factor. This is particularly true in the case of power switching devices where, as in the case of power metal oxide field effect transistors (MOSFETs), the on-resistance of these devices continues to decrease. For example, the parasitic resistance introduced by the bond wires and the lead frame in conventional packages becomes much more significant for such high current devices as power MOSFETs. Furthermore, the continuous shrinking of geometries and the resulting increase in chip densities increases the demand for semiconductor packages with lead counts higher than that offered by the conventional packaging techniques.
Ball grid array and flip chip technologies were developed to address some of these demands. Both of these technologies provide for a more direct connection between the silicon die and a circuit substrate as well as providing for higher interconnect densities.
In one method for fabricating a flip chip type semiconductor die package, a vertical MOSFET device is formed in a thick semiconductor wafer (e.g., 15 to 23 mils thick) (1 mil= 1/1000th of an inch). A solder mask with apertures is formed on the semiconductor wafer and solder balls are deposited in the apertures. The solder balls are reflowed so that they bond to the semiconductor wafer. The semiconductor wafer is then subjected to a lapping process where the wafer is thinned to, for example, 8 mils. The semiconductor wafer is then diced to form individual semiconductor dies.
A carrier for the die package is also prepared. Solder balls are deposited on the carrier. To help balls stay in place, the solder balls are partially reflowed and subsequently bond to the carrier. A “partial” reflow process is performed at a lower temperature and/or in less time than a full reflow process. A full reflow process is not performed, since performing a full reflow process causes the solder balls to collapse and lose their shape. Once the semiconductor die and the carrier are formed, the semiconductor die can be attached to the carrier using a die attach material. The carrier and the semiconductor die can then be flipped over and then mounted to a circuit substrate such as a printed circuit board (PCB).
A number of improvements could be made to this method. For example, using two separate steps to place solder balls on the semiconductor die and the carrier increases the cost and the processing time for the package. In addition, using two steps to place solder balls on the semiconductor die and the carrier can increase the likelihood that the bumps on the two components will not be coplanar. If the ends of the solder balls on the two components are not coplanar, then all of the solder balls may not all contact the conductive lands on a circuit substrate. If this happens, interconnects between the semiconductor die and the circuit substrate may not be formed. Moreover, because the solder balls on the carrier are partially reflowed, the bonds formed between the solder balls and the carrier are weaker than if a full reflow process were performed. It would be desirable to increase the strength of the bonds formed between the solder balls and the carrier in order to improve the reliability of the formed semiconductor die package.
Embodiments of the invention address these and other problems.